1. Technical Field
The present invention relates to a method and system for performing simulation in general, and in particular to a method and system for performing system verification of a device. Still more particularly, the present invention relates to a method and system for verifying a source-synchronous communication interface of a device.
2. Description of the Prior Art
Traditionally, a computer system contains various components that are interconnected with each other via pins and system traces. These components, such as processors, controllers, memories, etc., typically utilize fully-synchronous communication in which the same clock signal is used to drive and to receive interface signals. However, the speed of synchronous communication becomes a bottle-neck as interface operation frequency begins to increase. One solution to the communication speed problem is to utilize source-synchronous communication in which different clocks are used to drive and to receive interface signals.
With source-synchronous communication, a sending component sends a sample clock signal along with the group of data signals being transferred, and the sample clock signal is then used by the receiving component to sample the group of data signals. After sampling, the sampled signals must subsequently be transferred to the local clock domain of the receiving component. It has been observed that clock domain transfer problems often arise in logic circuit interfaces that are specifically designed for time critical source-synchronous communication. Therefore, a need exists for testing various aspects of source-synchronous communication during the design phase in order to verify proper logic implementation of those logic circuit interfaces. The present disclosure provides a method and system for verifying the proper functionality of a source-synchronous communication interface of a device, such as a processor.
In accordance with a preferred embodiment of the present invention, a software model of a first device having a source-synchronous communication interface and a software model of a second device capable of communicating with the first device via the source-synchronous communication interface are provided. The source-synchronous communication interface includes an applied clock line, an address line, an echo clock line, and a data line. A simulation of a data request from the first device model to the second device model via an applied clock signal along with an address on the applied clock line and the address line is initially performed. The requested data is then received by the first device model from the second device model via the data line after various delays between the applied clock signal and an echo clock signal on the applied clock line and the echo clock line, respectively. Finally, the requested data received by the first device model is verified as to its veracity.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.